1. Field of the Invention
The present invention relates to an operation apparatus, an operation apparatus control method, a program and a computer readable information recording medium, and, in particular, to a reconfigurable operation apparatus by which various sorts of processing are made to carry out as a result of the configuration thereof being dynamically changed, a control method therefor, a program including instructions for carrying out the method and a computer readable information recording medium storing therein the program.
2. Description of the Related Art
For example, Japanese Laid-open Patent Application No. 2001-312481 discloses an operation apparatus having reconfigurable operation devices in which a processing algorithm is changeable as a result of connection among the plurality of operation devices being appropriately switched. This operation apparatus includes a state management part and a plurality of processor elements which are electrically connected in a form of a two-dimensional array. This configuration is referred to as a tile, and, Japanese Laid-open Patent Application No. 2004-133781 discloses a configuration in which a plurality of such tiles are provided. Data transfer among the tiles when the plurality of tiles are provided is carried out through transfer relay circuits being disposed among the tiles (see FIGS. 7, 8 and 9 of Japanese Laid-open Patent Application No. 2004-133781).
The transfer relay circuit is a double-directional tri-state buffer, and, the term ‘buffer’ therein means an amplifier in this case. Turning on/off thereof is controlled by a central control part which is provided separately from the tiles, or, in some case, is controlled by a state management part included in either one of the adjacent tiles. The plurality of the transfer relay circuits are provided between the pair of adjacent tiles. However, Japanese Laid-open Patent Application No. 2004-133781 does not particularly disclose how data lines of one of these tiles and data lines of the other tile are connected by the transfer relay circuits.
In other words, which data line in the other tile is connected with one data line of the one tile is not clearly disclosed. It is assumed that, one data line in the one tile is connected to a fixedly determined data line in the other tile through the transfer relay circuit. This is because, according to Japanese Laid-open Patent Application No. 2004-133781, such a configuration may be applied that direct connection is applied between some data lines, while some other data lines are connected via the transfer relay circuit.
Instead of such a transfer relay circuit, a common resource may be provided between adjacent tiles according to Japanese Laid-open Patent Application No. 2004-133781, FIG. 18. However, for this example, since further details are not disclosed while it is mentioned that a temporary holding circuit may be provided, a specific configuration thereof is not clear. Further, Japanese Laid-open Patent Application No. 2004-133781 also discloses an example in which both the transfer relay circuit and the common resource are provided (see FIG. 21 of the document).
Japanese Laid-open Patent Application No. 5-108586 discloses an operation apparatus having a plurality of processor elements. According to the document, an alternate buffer (in other words, a double buffer) is necessarily provided for communication between the processor elements, and therethrough, data transfer is carried out (see FIG. 6). A reason why such an alternate buffer is required is described next. Normally, in processing in a plurality of independent processors (having no common program counter thereamong), progress timing does not coincide thereamong even when beginning timing is made to coincide, in general, unless no dependent relationship exist thereamong at all, and also, the completely same processing is carried out. Such a relation of operation is referred to as an ‘asynchronous operation’, hereinafter. Therefore, timing at which one operation processor carries out data processing in a processor element does not coincide with progress timing of anther operation processor even in the same processor element, which processor communicates data with the other processor (asynchronous operation). Therefore, the asynchronous operation can be carried out properly provided that, during an interval in which one processor writes in one memory of the above-mentioned alternate buffer, the other processor reads out from the other memory of the same alternate buffer.